By Balsha R. Stanisic
In the early days of VLSI, the layout of the facility distribution for an built-in cir cuit was once particularly easy. energy distribution --the layout of the geometric topology for the community of wires that attach a few of the energy provides, the widths of the indi vidual segments for every of those wires, the quantity and placement of the facility I/O pins round the outer edge of the chip --was uncomplicated as the chips have been easier. Few to be had wiring layers pressured floorplans that allowed easy, planar (non-over lapping) strength networks. decrease speeds and circuit density made the alternative of the cord widths more straightforward: we made them simply fats adequate to prevent resistive voltage drops because of switching currents within the offer community. And we simply did not want huge, immense num bers of energy and floor pins at the package deal for the chips to paintings. it isn't so basic from now on. elevated integration has pressured us to target reliability matters corresponding to steel elec tromigration, which impacts twine sizing judgements within the strength community. additional steel layers have allowed extra flexibility within the topological format of the ability networks.
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Extra info for Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
We begin this chapter with the highest level physical design component decision, design style selection. 2 Design Style Selection We discussed two basic design styles in the previous chapter and found the custom macrocell 2-D design style the most popular in analog power bus synthesis methods. We also saw 1wo flavors for this design style. We choose the slicing style because it contains a channel representation. Recall from Chapter 2, the flat style could also be used, but WOUld require a channel identification preprocessing phase.
Next, noise coupled to an analog power supply causes problems because even designs using the best differential design techniques have finite power supply rejection. 6. Sensitive Analog + Noisy Digital noise path Substrate ,/· · ·. t, Interconnect chi·p=p~~k~·g~"·"" """''''''''''''''''''''''''''''''--, '\ Ltxnfs J ... 6 Mixed-signal power supply noise generation and coupling. The digital logic switching activity generates inductive noise which couples through the common chip substrate to the analog portion of the chip.
From the manually assigned power 110 cells, existing power bus synthesis methods first determine a power bus topology. Then, other methods are used to size the individual power bus segments for that fixed topology. Some of the earliest tools used simple heuristics to accomplish both phases of power bus synthesis. Initially, the tools assumed a single pad each for power and ground and a single layer for routing these nets. This required planar routing and tree topologies for nets. 13] synthesized the power distribution by first determining a feasible power and ground tree topology.
Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs by Balsha R. Stanisic